The production and quality control processes used by semiconductor device manufacturers and material producers, among others, often require an accurate knowledge of wafer characteristics such as flatness, diameter, thickness, bow, warp, and resistivity, among others.
Automated, high-throughput assembly line systems may be employed to obtain the desired information on wafer characteristics. For example, in order to evaluate the flatness of a wafer, typically, the wafers are moved into a wafer flatness station. The flatness station is operated to provide information representative of the degree of flatness or deviation from a planar or other intended surface, for each wafer. Such information may be advantageously utilized, for example, during the various phases of photolithographic processing typically employed in electronic circuit device fabrication.
Conventionally, semiconductor wafer flatness is determined by evaluating the deviation of a wafer surface relative to a defined surface, called herein the deviation surface. The flatness parameters involved in the conventional evaluation of semiconductor wafers include global or local evaluation of the wafer, definition of the surface from which deviation from the wafer will be evaluated, and presentation format of the metrics calculation. Some options for the parameters, described below, are outlined in SEMI STD M1-1103, SPECIFICATIONS FOR POLISHED MONOCRYSTALLINE SILICON (©SEMI 1978, 2003) (hereinafter SEMI STD M1-1103).
SEMI STD M1-1103 contains dimensional and crystallographic orientation characteristics and limits on surface defects for semiconductor wafers. It specifies that wafer flatness should be determined either by the method outlined in ASTM Test Method F1530 or by another method as agreed upon between the supplier and the purchaser. ASTM Test Method F1530 is now known as SEMI STD MF1530-02, TEST METHOD FOR MEASURING FLATNESS, THICKNESS, AND THICKNESS VARIATION ON SILICON WAFERS BY AUTOMATED NONCONTACT SCANNING (© SEMI) (hereinafter SEMI MF1530-02).
SEMI MF1530-02 specifies determining flatness of a wafer as it would appear relative to a specified reference plane when the back surface is ideally flat, as when pulled down onto an ideally clean, flat chuck. In the method described therein, an opposed pair of probes scans the front and back surface along a prescribed pattern. The data so obtained is constructed into a thickness data array, which represents the front surface as it would appear when the back surface is ideally flat. With the definition of an evaluation area and a reference plane, the thickness data array may be used to calculate surface flatness of the wafer within the evaluation area. An analogous wafer evaluating method is also described in U.S. Pat. No. 4,860,229, issued Aug. 22, 1989, and entitled WAFER FLATNESS STATION, which is hereby incorporated by reference.
An illustrative semiconductor wafer surface 100 for which flatness could be evaluated in accordance with SEMI STD M1-1103 and SEMI MF1530-02 is shown in FIG. 1. The surface 100 has a front surface F, a back surface B, an edge 150, and a fixed quality area 120, also known as FQA 120, which is the central area of a wafer surface 100 and an area of chief interest to manufacturers. The wafer surface area outside the FQA 120 is the edge exclusion region 140, defined by an edge exclusion, XX, extending inwardly from the edge 150. Currently, common edge exclusion is 2-3 mm. As semiconductor production improves, the length of the edge exclusion is expected to decrease. The Semiconductor Industry Association predicts that the edge exclusion length will be 1 mm by the year 2007.
Typically, the wafer surface is organized into a Cartesian grid of sites having areas measuring, for example, 26 mm by 8 mm. FIG. 2 shows a portion of a Cartesian grid defined (but not shown to scale) on the wafer of FIG. 1. Sites are defined to be rectangular areas with centers that fall within the FQA 120. Areas in FIG. 2 with centers (represented by a point) within FQA 120 that are defined as sites include sites 13a and 13b. Areas in FIG. 2 with centers (represented by a point) outside of FQA 120 that are not defined as sites include non-site areas 13c and 13d. 
Which evaluation area and deviation surface to choose in order to judge flatness depends upon the specifications of the electronic circuit device fabrication system for which the wafer is intended, for example a photolithographic processing system. Both SEMI STD M1-1103 and SEMI MF1530-02 specify that the wafer evaluation area could be defined by site, also known as “S”; or globally (encompassing the entire wafer), also known as “G”. They also specify relative to which wafer surface the deviation should be evaluated: the front surface, also known as “F”, or the back surface, also known as “B”.
SEMI STD M1-1103 and SEMI MF1530-02 then identify four options for specifying a reference plane: an ideal back surface (equivalent to the ideally flat surface of a chuck that is holding the surface), also known as “I”; or a plane defined by three points at specified locations on the front surface F of the wafer surface 100, also known as “3”; or a plane defined by a least-squares fit to the front surface F using all points of a fixed quality area on the wafer surface 100, also known as “L”; or a plane defined by a least-squares fit to the front surface F within a site 13a, 13b, also known as “Q”.
A suitable deviation surface from which deviation may be evaluated is then identified. For example, the deviation surface could be coincident with the reference plane. Alternatively, while it is not necessary, the deviation surface could be defined, as in SEMI STD M1-1103 and SEMI MF1530-02, to be that plane parallel to the reference plane but having zero deviation from the wafer surface at the center point of the evaluation area.
Deviation is then calculated point by point between the surface of the wafer and the deviation surface. Finally, the deviation is presented either as the range of deviation from the reference plane, also known as “R”; or as the maximum deviation from the reference plane, also known as “D”.
One common set of conditions used by manufacturers to evaluate flatness is known as SFQR:                S=the wafer is evaluated by sites on the wafer;        F=the reference plane is constructed relative to the front surface of the wafer;        Q=the reference plane is defined by a least-squares fit to the front surface using all points of a site 13a; and        R=the results are presented as the range of deviation from the deviation surface.        
A significant drawback to using the conventional methods to evaluate semiconductor wafer flatness is that the test methods of U.S. Pat. No. 4,860,229, SEMI STD M1-1103 and SEMI MF1530-02 specifically cover procedures that, once the FQA 120 is defined, evaluate the flatness of the wafer in such a way that the boundary of the wafer is not considered. The flatness evaluation methods defined therein are defined intentionally to evaluate flatness independent of wafer boundary. However, given that wafers do have a boundary, wafer boundary affects flatness evaluation, especially within the area of the FQA 120 near the edge exclusion region 140. Flatness evaluation of such area using the test methods of U.S. Pat. No. 4,860,229, SEMI STD M1-1103 and SEMI MF1530-02 will be incomplete and inexact. Further, the imposition of a grid defined by Cartesian coordinates upon a generally disc-shaped surface results in sites of different geometries and orientation relative to each other.
Referring to FIG. 2, because semiconductor wafers are generally disc-shaped, a portion of the area of certain sites will be beyond the FQA 120 or even beyond the edge 150 of the wafer. A site having its entire area falling within the FQA 120, such as site 13a, is called a full site, and a site without its entire area falling within the FQA 120, such as site 13b, is called a partial site. While SEMI STD M1-1103 and SEMI MF1530-02 provide for optional inclusion or exclusion of partial sites in flatness evaluation, non-site areas near or at the edges of the wafer are not evaluated.
Referring to FIG. 2, a grid area having a center that falls outside the FQA 120, such as area 13c (which has a center within edge exclusion region 140) or area 13d (which has a center beyond the edge 150), is not considered a site, and is typically not evaluated. Therefore, limitations in the definitions outlined in SEMI STD M1-1103 of areas near or at the edge cause evaluation of flatness near or at the edge to be incomplete and inexact.
Further, the characteristics of rectangular sites situated in similar radial locations on the wafer surface 100 will not be comparable, because the orientation of those areas with respect to the wafer is dissimilar. For example, referring to FIG. 1, sites 13e, 13f (not shown to scale) are both located close to the edge 150 but at a radial location 90 degrees apart. As can be seen in FIG. 1, the areas of sites 13e, 13f are not oriented similarly on the wafer surface 100. Most of the area of site 13e is close to the edge 150, while more of the area of site 13f is internal to the wafer surface 100. Therefore, the metrics from the sites 13e, 13f will not be comparable, because the evaluation areas on the sites 13e, 13f are not comparable, given the disc shape of the wafer.
If, for example, the wafer surface 100 has a topographical feature, such as a ridge 51, a portion of which is shown generally as a dashed line in FIG. 1, that extends around the wafer surface 100 circumferentially but interior to the wafer edge, the feature would extend across the rectangular sites 13e, 13f at different locations. The rectangular site 13e, 13f would provide a different measure of certain metrics, such as SFQR. In addition, data values about the ridge 51 on the wafers 13e, 13f would not be comparable because the data locations of the ridge 51 on the sites 13e, 13f are not comparable. The methods described above do not take account of the edge of the wafer, in particular its radius, and how wafer edge affects the area being evaluated, despite the importance of the wafer edge to the evaluation of flatness in certain regions of the wafer.
Thus, it is apparent that the methods described above do not define methods that provide appropriate characterization of a semiconductor wafer near or at its edge, that provide exact characterization of a semiconductor wafer relative to its edge, or that allow comparison between or among selected areas of a wafer relative to their location on the wafer relative to the edge
With the development of improved photolithography methods, characterizing a semiconductor wafer near and at its edge is becoming of increasing importance. Edge flatness evaluation methodologies, which are not defined by SEMI STD M1-1103 and which provide information about the amount of roll off of the wafer surface at or near the edge, as compared to the surface within the FQA 120, have been developed.
One such system is described in Kimura et al., “A New Method for the Precise Measurement of Wafer Roll Off of Silicon Polished Wafer”, 38 Jpn. J. Appl. Phy. 38 (1999). In Kimura, a stylus profiler and a block gauge evaluate the profile of a wafer's surface (known as edge roll off) near the edge of the wafer. A wafer is placed on an optical flat so that the physical edge of the wafer touches a block gauge. The stylus of the profiler moves along the block gauge, and drops off the gauge at the physical edge of the wafer. As the stylus moves along the surface of the wafer toward the center, it measures the displacement z between the actual height of the wafer within the FQA and the height of the wafer below the stylus. Kimura defines a metric known as the roll off amount (ROA), which is the amount of displacement z relative to a reference line when the stylus is located 1 mm from the physical edge.
Another system is described in U.S. Ser. No. 10/203,882, entitled Wafer Shape Evaluating Method and Device Producing Method, Wafer and Wafer Selecting Method, filed Nov. 15, 2001 (hereinafter “Kobayashi et al.”). In Kobayashi et al., the flatness of an area at a wafer's edge is determined by extrapolating known surface characteristics into areas having unknown characteristics. A first region is provided within a wafer surface, and a reference line or a reference plane is calculated in the first region. A second region is then provided outside the first region, and the reference line/plane is extrapolated into the second region. Finally, the displacement z is determined between the configuration of the second region and the reference line/plane within the second region.
While the Kimura et al. and Kobayashi et al. methodologies provide some evaluation of the wafer edge that would not otherwise be able to be evaluated, their usage poses certain difficulties. They neither develop metrics nor statistics relating to the topography of the surface of wafer regions near or at the wafer edge. Therefore, their uses in wafer characterization of the edge are limited.
Other systems evaluate the edge of a wafer. Found in the field of edge profilometry, systems such as those developed by Chapman Instruments develop a two-dimensional profile of radial segments around an edge, providing a 2-D data set for a line extending along the radius of an edge and the displacement z from the line and an ideal line extending from the internal part of the wafer. While edge profilometers are thus able to map roll-off of radial lines near the edge of a wafer, like Kimura et al. and Kobayashi et al., they develop neither metrics nor statistics relating to the topography of the surface of wafer regions at or near a wafer edge. Therefore, their uses in wafer characterization of the edge are also limited.
It is therefore desirable to provide an improved methodology for evaluating the flatness of a semiconductor wafer, in particular to provide a methodology for evaluating the flatness of the entire extent of a semiconductor wafer.
Further, it is desirable to provide a methodology for accurate and complete evaluation of the flatness of a wafer at and near its edges, including the areas of a wafer that would not obtain complete and exact characterization should a conventional flatness evaluating technique be applied to the wafer.
Finally, it is desirable to provide a methodology for evaluating the flatness of a semiconductor wafer to allow comparison between or among selected areas of a wafer that are definable with respect to the edge of the wafer.